Overview
The overall goal of this project was to develop a working MIPS-compatible CPU that will interface using a memory-mapped bus, which would give it access to memory and other peripherals. This was implemented in Verilog which ultimately could have been manufactured.
This project contains two main components:
- MIPS CPU written in Verilog
- Test bench written in Shell containing extensive test cases
Point at or tap a block to see what it does.
- 1 · Fetch
- 2 · Decode
- 3 · Execute
- 4 · Write back
A MIPS CPU, built from scratch
MIPS is a RISC instruction set: a small set of simple 32-bit instructions that hardware can run quickly. The name stands for Microprocessor without Interlocked Pipeline Stages.
What makes this design different
The core uses a Harvard architecture, with separate paths for instructions and data. It can fetch the next instruction and read or write data at the same time, so each instruction finishes in one clock cycle and the control logic stays simple. But the brief asked for a CPU on one shared Avalon memory bus, where instructions and data take turns. So we kept the simple Harvard core and put an adapter around it: the bus wrapper. The wrapper fetches the instruction and the data one after the other, and pauses the core while it waits. To the core, it still looks like two separate memories.